1. Field of the Invention
The present invention relates to DC power supply systems, and more particularly to a controller for a multiphase DC-DC converter which employs a single external resistor for setting gain for multiple channels.
2. Description of the Related Art
Electrical power for an integrated circuit (IC) is typically supplied by one or more direct current (DC) sources. FIG. 1 is a simplified schematic and block diagram of a multi-phase buck-mode pulse width modulation (PWM) DC-DC converter 100 of prior art. The converter 100 includes a PWM controller 101 which provides multiple synchronous PWM signals PWM1, PWM2, PWM3 and PWM4 to four driver and switch circuits 103, individually labeled DSC1, DSC2, DSC3 and DSC4, respectively. Each driver and switch circuit 103 has an output coupled to a common output node 105, which develops an output signal VOUT applied to a load 107 and to a load reservoir capacitor 109, both referenced to a power supply rail (e.g., GND). The VOUT signal is fed back via a feedback resistor RFB to the PWM controller 101. Each of the driver and switch circuits DSC1, DSC2, DSC3 and DSC4 is coupled to the PWM controller 101 via a corresponding one of current sense resistors RS1, RS2, RS3 and RS4, respectively. Although the converter 100 shows four different driver and switch circuits 103 for implementing up to four phases, it is understood that a different number of phases may be employed.
Only the driver and switch circuit DS1 is described in further detail, where it is understood that all of the driver and switch circuits 103 are configured in substantially the same manner. The PWM1 signal is provided to a driver 111 of the driver and switch circuit DS1, where the driver 111 controls the turn-on and turn-off of a pair of electronic power switching devices 113 and 115. In particular, the driver 111 generates an upper gate switching signal UGATE provided to the control terminal (e.g., gate) of the upper (or high side) switch 113 and a lower gate switching signal LGATE provided to the control terminal of the lower (or low side) switch 115. In the particular configuration shown, the switches 113 and 115 are depicted as N-channel metal-oxide semiconductor field-effect transistors (MOSFETs) having their drain-source current paths coupled in series between a pair of power supply rails (e.g., VIN and ground (GND)). The drain of switch 113 is coupled to the source of switch 115 at a phase node 117, which is coupled to one end of an output inductor 119. The other end of the inductor 119 is coupled to the output node 105. The phase node 117 develops a signal PHASE fed back to the driver 111, where the PHASE signal is monitored for adaptive shoot-through protection and also provides a return path for the upper gate drive. The phase node 117 is also coupled to the sense resistor RS1 fed back to the PWM controller 101. The driver and switch circuits DSC2, DSC3 and DSC4 are configured in the same manner and are coupled to the current sense resistors RS2, RS3 and RS4, respectively, fed back to the PWM controller 101.
The PWM controller 101 includes a voltage error amplifier circuit 121, PWM logic 123 and a current sense circuit 125. The resistor RFB is coupled to the voltage error amplifier circuit 121 and the current sense resistors RS1–RS4 are coupled to the current sense circuit 125. The voltage error amplifier circuit 121 and the current sense circuit 125 are coupled to each other and to the PWM logic 123, which adjusts the duty ratio of the PWM1–PWM4 signals to maintain the node 105 within a prescribed set of parameters. The parameters might include, for example, a droop or gain parameter defining a fixed ratio amount that the voltage of VOUT decreases in response to increasing load current. One particularly useful circuit for performing this current sensing operation is disclosed in U.S. Pat. No. 6,246,220 entitled “Synchronous-Rectified DC to DC Converter With Improved Current Sensing” to Isham et al., which is assigned to the same assignee of the present application and which is incorporated herein by reference in its entirety (hereinafter referred to as the '220 patent).
FIG. 2 is a simplified schematic diagram of a portion of the PWM controller 100 implemented as described in the '220 patent (e.g., a portion of the current sense circuit 125 and the voltage error amplifier circuit 121). The illustrated circuit includes a virtual ground amplifier 201 having an inverting input coupled to node 202, which is coupled through a corresponding sense resistor RS1 (e.g., representing any of the current sense resistors RS1–RS4) to output node 105. The amplifier 201 has a non-inverting input coupled to ground and an output coupled to a control terminal of a variable impedance device, which is the gate of an N-channel field-effect transistor (NFET) 203 in the embodiment shown. The drain and source of the NFET 203 is coupled between the inverting input of the amplifier 201 and a sample and hold circuit 207 at a node 205.
The sample and hold circuit 207 is implemented with a pair of P-channel FETs P1 and P2, a capacitor C1 and a single-pole, single-throw (SPST) switch SW. The drain of P1 is coupled to a DC source voltage VCC and its gate and source are coupled together at one terminal of the switch S1 at node 205. The other terminal of the switch SW is coupled to the gate of P2 and to one end of the capacitor C1, having its other end coupled to VCC. The drain of P2 is coupled to VCC and its source is coupled to a node 209, which is further coupled to the inverting input of a voltage error amplifier 211 and to one end of the resistor RFB. The non-inverting input of amplifier 211 receives a reference voltage from a voltage source 213 (shown as a digital to analog converter or DAC), and the output of amplifier 211 is coupled to a node 215 to enable connection of a feedback RC circuit to node 209. The output of the amplifier 211 generates an error signal ERR which is provided to comparators (not shown) of the PWM logic 123 for controlling the output voltage VOUT.
In operation, the drain-source impedance of the NFET 203 is varied as controlled by the output of the amplifier 201 in a direction to hold one end of the resistor RS1 at virtual ground. The other end of the resistor RS1, coupled to the output node 105, is at a voltage equal to the load current (LC) times the on-state drain-to-source resistance (RDSON) of the low side switch of the corresponding driver and switch circuit 103, such as the switch 115. This causes current to flow through the NFET 203 that is equal to RDSON*LC/RS1 (where the asterisk “/” denotes multiplication and the forward slash “/” denotes division). The sample and hold circuit 207 samples this current flowing through the NFET 203 and applies it through resistor RFB, which causes a voltage drop across RFB equal to RDSON*LC*RFB/RS1. The current sense and sampling portion of the circuit 200 may be repeated for each of the other sense resistors RS2–RS4 to provide gain control for each of the four phases of the multiphase converter 100 in a similar manner.
In this manner, the gain (i.e., the amount that VOUT decreases relative to output current) is established by the ratio of the value of the applicable current sense resistor RSx (e.g., representing the resistors RS1–RS4) to the value of the feedback resistor RFB. The PWM controller 101 may be implemented on a separate integrated circuit (IC) in which the resistor RFB and each of the resistors RSx are external to that IC. Nodes 202, 209 and 215 are coupled to or otherwise form pins of the IC. This allows a user to adjust the values and ratios of these resistors to thereby adjust the gain of the converter 100. While this may be acceptable for a single channel device, it causes a relatively onerous pin requirement for a multiphase system. Note, for example, that instead of a single pin node 202, four separate pins 101a, 101b, 101c and 110d are required to connect the four separate resistors RS1–RS4, respectively, to the current sense circuit 125. In some configurations, the driver 111 may be incorporated within the same IC as the PWM controller 101, so that the phase node 117 is also internally available. Nonetheless, in the configuration shown, four separate current sense resistors and four separate pins 101a–101d would still be needed to provide the user the same flexible value and ratio adjustment.